A CMOS Antenna-to-Bits 230-mW 120-Gbps F-band Receiver with Analog-Domain 64QAM Detection and Extraction

The design and implementation of a fully integrated CMOS antenna-to-bits 100 - 140 GHz receiver (RX) realizing 64QAM demodulation in analog-domain is presented. A sequential asynchronous QAM demodulation method is proposed that allows symbol detection, recovery, and extraction at 120-Gbps data rate at remarkably low power consumption. Fabricated in a 22-nm FDSOI CMOS process, this 100-140-GHz CMOS RX exhibits a measured maximum conversion gain of 32 dB and a minimum noise figure (NF) of 9.5 dB. A data rate of 120 Gbps is wirelessly measured at 15-cm distance with the received 64QAM signal being directly demodulated on-chip at a bit-error rate (BER) of 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−2</sup>. The measured RX sensitivity at this BER is -32 dBm. The prototype occupies 2.5 × 3mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of die area, including PADs and test circuits and consumes a total dc power of 230 m W.

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Publication Details

Published
2025-06-08
DOI
https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075138
Citations
2
Primary Topic
Radio Frequency Integrated Circuit Design
Type
article
Field-Weighted Citation Impact
1.46

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article

A CMOS Antenna-to-Bits 230-mW 120-Gbps F-band Receiver with Analog-Domain 64QAM Detection and Extraction

Payam Heydari, Mohammad Oveisi, Zisong Wang, Youssef O. Hassan
2 citations
Radio Frequency Integrated Circuit Design
1.46
article

A CMOS Antenna-to-Bits 230-mW 120-Gbps F-band Receiver with Analog-Domain 64QAM Detection and Extraction

Payam Heydari, Mohammad Oveisi, Zisong Wang, Youssef O. Hassan
article en
2 citations

Abstract

The design and implementation of a fully integrated CMOS antenna-to-bits 100 - 140 GHz receiver (RX) realizing 64QAM demodulation in analog-domain is presented. A sequential asynchronous QAM demodulation method is proposed that allows symbol detection, recovery, and extraction at 120-Gbps data rate at remarkably low power consumption. Fabricated in a 22-nm FDSOI CMOS process, this 100-140-GHz CMOS RX exhibits a measured maximum conversion gain of 32 dB and a minimum noise figure (NF) of 9.5 dB. A data rate of 120 Gbps is wirelessly measured at 15-cm distance with the received 64QAM signal being directly demodulated on-chip at a bit-error rate (BER) of 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−2</sup>. The measured RX sensitivity at this BER is -32 dBm. The prototype occupies 2.5 × 3mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of die area, including PADs and test circuits and consumes a total dc power of 230 m W.

University of California, Irvine (US), Marvell (United States) (US), Marvell (Israel) (IL)
National Science Foundation
Affordable and clean energy
Openalex Percentile: Top 16%
Radio Frequency Integrated Circuit Design
1.46
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