Monolithic CFET Flow Improvements Integrating Cover Spacer and Dual-WF RMG

We report on various modifications made to our monolithic-CFET process flow resulting in significant improvements in drive current and CMOS survival rate (SR) (from 5% to 30%). We share our implementation of dual Work Function Metal (WFM) vertical patterning using carbon-based soft mask inside the gate trench integrating TiN and TiAl metals. The quality of the Source-Drain (SD) junctions are improved by implementation of a sacrificial Cover Spacer (CSP) using a vertically patterned sidewall ALD hardmask (HM) covering top device Si channel. Contact pattern placement accuracy is improved at tight gate pitch using a low stress film. pFET via resistance benefit from implementing a dedicated tungsten oxide (WOx) wet etch step. Finally, we discuss ideas with potential for further pFET SR improvements by re-engineering the bottom junction (BJ) and BackSide Contact (BSC) formation involving impact of backside formed bottom dielectric isolation (BS-BDI).

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Published
2025-06-08
DOI
https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075156
Citations
1
Primary Topic
Advancements in Semiconductor Devices and Circuit Design
Type
article
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Monolithic CFET Flow Improvements Integrating Cover Spacer and Dual-WF RMG

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Monolithic CFET Flow Improvements Integrating Cover Spacer and Dual-WF RMG

Chuanxiang Sheng, Maria V. Chistiakova, A. Vandooren, S. Biesemans, Farid Sebaai, Naveen Reddy, S. Subramanian, Hans Mertens, A. Sepulveda Marquez, Rajendra K. Saroj, Harinarayanan Puliyalil, Daniel Álvarez, P. Puttarame Gowda, Violeta Georgieva, Y. Kimura, H. Arimura, Efrain Altamirano Sánchez, Alina Arslanova, Naoto Horiguchi, Dmitry Batuk, Annika H. G. Peter, Karen Stiers, Sujan K. Sarkar, S. Choudhury, T. Chiarella, A. Mingardi, S. Demuynck, Maryam Hosseini, Tanmoy Sarkar, An Peng, Jérôme Mitard, J. G. Lai, C. Cavalcante, Lucas Petersen Barbosa Lima, I. Gyo Koo
article en
1 citations

Abstract

We report on various modifications made to our monolithic-CFET process flow resulting in significant improvements in drive current and CMOS survival rate (SR) (from 5% to 30%). We share our implementation of dual Work Function Metal (WFM) vertical patterning using carbon-based soft mask inside the gate trench integrating TiN and TiAl metals. The quality of the Source-Drain (SD) junctions are improved by implementation of a sacrificial Cover Spacer (CSP) using a vertically patterned sidewall ALD hardmask (HM) covering top device Si channel. Contact pattern placement accuracy is improved at tight gate pitch using a low stress film. pFET via resistance benefit from implementing a dedicated tungsten oxide (WOx) wet etch step. Finally, we discuss ideas with potential for further pFET SR improvements by re-engineering the bottom junction (BJ) and BackSide Contact (BSC) formation involving impact of backside formed bottom dielectric isolation (BS-BDI).

IMEC (BE)
Openalex Percentile: Top 25%
Advancements in Semiconductor Devices and Circuit Design
0.73
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