EVA: A 16mm<sup>2</sup> 1.54TFLOPS Tiled-Based Accelerator for Evolvable Edge Computing
EVA is an accelerator designed for evolvable edge computing applications. It integrates programmable processing array tiles (A-Tiles) for performance and utilization, and RISC-V CPU tiles (C-Tiles) for control and quick reconfiguration at a 100ns timescale. EVA features a versatile interconnect fabric, a distributed memory system, and flexible mapping. A 16mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> EVA test chip achieves a throughput of 1.54TFLOPS (FP16) at 0.9V and a peak energy efficiency of 708GFLOPS/W at 0.49V, demonstrating high compute density and efficiency for diverse workloads.
Authors
- Junkang Zhu (ORCID: https://orcid.org/0000-0002-4296-1358)
- M. Kim (ORCID: https://orcid.org/0000-0003-4506-7930)
- Zhengya Zhang (ORCID: https://orcid.org/0000-0001-5963-9018)
- Wei Tang (ORCID: https://orcid.org/0000-0001-8613-4285)
- Cheng‐Hsun Lu (ORCID: https://orcid.org/0000-0002-4794-9438)
- Tianyu Wei (ORCID: https://orcid.org/0000-0002-8251-8107)
Institutions
- University of Michigan (US)
Publication Details
- Published
- 2025-06-08
- DOI
- https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075176
- Primary Topic
- Neural Networks and Reservoir Computing
- Type
- article
- Field-Weighted Citation Impact
- 0.00