A Generalizable Tri-Layer Design Framework for Enhancing OSFET Reliability

In this work, we propose a Tri-Layer structure design methodology to systematically enhance the reliability performance of oxide semiconductor (OS) FETs, applicable across various OSFET technologies. This approach addresses longstanding reliability challenges of positive and negative bias temperature instability (P/NBTI) in a comprehensive and simultaneous manner. The Tri-Layer incorporates a top layer and a passivation layer, each with distinct roles: the top layer functions as a hydrogen (H) reservoir, mitigating H effect and alleviating quantum confinement effects (QCE) through bandgap relaxation, while the passivation layer acts as an H barrier, preventing H diffusion from the ambient environment. The independent tunability of these layers allows for material property optimization, improving reliability without sacrificing electrical performance. To validate this methodology, we fabricated In-Ga-Zn-Sn-O (IGZTO) Tri-Layer FETs, achieving a record-low threshold voltage change (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta V_{\text {th }}$</tex>) per oxide electric field (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$E_{\text{OX}}$</tex>) of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.009 ~\mathrm{V} \cdot ~\text{cm} / \text{MV}$</tex> at high temperature (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$T$</tex>) of 360 K with stress time of 700 s under NBTI condition.