A Single-Channel 14B 3GS/s Pipelined ADC in 28nm Technology

This article presents a negative-delayed-input (NDI)-assisted Pipelined ADC (Pipe), which considerably shrinks the critical path by enabling concurrent quantization in all stages. The single-channel (1-CH) 14b ADC runs at 3GS/s and achieves 62.3 dB SNDR and 81.1 dB SFDR at Nyquist input after uneven-spaced (UE) PWL function INL calibration.

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Publication Details

Published
2025-06-08
DOI
https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074891
Citations
2
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
Field-Weighted Citation Impact
1.35
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article

A Single-Channel 14B 3GS/s Pipelined ADC in 28nm Technology

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2 citations
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article

A Single-Channel 14B 3GS/s Pipelined ADC in 28nm Technology

Chi–Hang Chan, Xianghui Pan, Buhui Rui, Yao Lu, Yan Zhu, Rui P. Martins
article en
2 citations

Abstract

This article presents a negative-delayed-input (NDI)-assisted Pipelined ADC (Pipe), which considerably shrinks the critical path by enabling concurrent quantization in all stages. The single-channel (1-CH) 14b ADC runs at 3GS/s and achieves 62.3 dB SNDR and 81.1 dB SFDR at Nyquist input after uneven-spaced (UE) PWL function INL calibration.

University of Macau (MO)
Affordable and clean energy
Openalex Percentile: Top 18%
Analog and Mixed-Signal Circuit Design
1.35
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