A 6.4GHz Fractional-N PLL with 96.6fs_rms Jitter and -257.4dB FoM

This paper presents a 6.4GHz DTC-based fractional-N sampling PLL with 96.6 fs<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</inf> jitter -65dBc fractional spurs and -257.4dB FoM. A gated-LMS-based calibration technique is used for both DTC gain and nonlinearity background calibration, eliminating the need for an auxiliary DTC to reduce power consumption and minimize calibration errors. Additionally, an SPD is designed to double the sign-comparison accuracy, further reducing calibration errors in DTC calibration.