A High-Order Masking with Load-Delay-Equalized WDDL for Provable Side-Channel Security
A custom WDDL is proposed for provably secure high-order masking. XOR/AND used in WDDL are designed by symmetric Pass Transistor Logic (PTL) to suppress data dependency in power/delay. A self-retimer is introduced to avoid accumulation of inter-stage power/delay variations due to unbalanced layout and routings. Those custom circuit techniques reduce data-dependent information leakage and non-ideal leakage due to unwanted coupling through supply and ground for proven high-order side-channel security.
Authors
- Takeshi Sugawara (ORCID: https://orcid.org/0000-0001-9356-534X)
- Takuya Wadatsumi (ORCID: https://orcid.org/0000-0003-3062-9523)
- Kazuki Monta (ORCID: https://orcid.org/0000-0003-1590-4822)
- Noriyuki Miura (ORCID: https://orcid.org/0000-0002-0072-6114)
- Makoto Nagata (ORCID: https://orcid.org/0000-0002-0625-9107)
- Yukihito Hiraga
- Jun Shiomi (ORCID: https://orcid.org/0000-0003-2733-9349)
Institutions
- University of Electro-Communications (JP)
- Kobe University (JP)
- The University of Osaka (JP)
Publication Details
- Published
- 2025-06-08
- DOI
- https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075152
- Citations
- 1
- Primary Topic
- Cryptographic Implementations and Security
- Type
- article
- Field-Weighted Citation Impact
- 2.48