Multi-Stack InTe Selector-Only Memory (SOM) Achieving Ultra-Low Power Operation $(\mathbf{10}\ \boldsymbol{\mu} \mathbf{A})$ and Excellent Endurance ($\sim \mathbf{10}^{\mathbf{10}}$ cycles)

We present an innovative In-Te based selector-only memory (SOM) featuring a multi-stack architecture that significantly boosts power efficiency and reliability. Through XPS, Raman spectroscopy and DFT simulation, we clarified how optimized In-Te bonding and trap engineering enable successful SOM operation while reducing write current <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{I}_{\text{write}})$</tex> to an ultra-low <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$10\ \mu \mathrm{A}$</tex>. This approach also resulted in a sufficient memory window (MW ~ 1 V), minimized variability, and achieved excellent endurance (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$-10^{10}$</tex> cycles).