Key to Low Supply Voltage: Transition Region of Oxide Semiconductor Transistors

We study the voltage transition region (TR) from sub- to above-threshold of field-effect transistors (FETs) and characterize its width (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{TR}}$</tex>) which informs how much the supply voltage (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{DD}}$</tex>) can be reduced. The TR is significant in amorphous oxide semiconductor field-effect transistors (OSFETs) because the shallow traps in amorphous OS channels lead to large <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text {TR }}$</tex>. We introduce a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text {TR }}$</tex> extraction scheme and identify four main sources of shallow traps (ST) in amorphous OSFETs. We design experiments to individually evaluate their impact on <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text {TR }}$</tex> and successfully devise four OSFET process/design knobs to minimize V TR. Our analysis is then extended to other prominent FETs in the literature, with crystalline channel FETs showing <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{TR}}&lt;80 \text{mV}$</tex>, in contrast to amorphous OSFETs with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text {TR }}$</tex> ranging from 160 mV to as high as 1.1 V, highlighting that <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{TR}}$</tex> in amorphous OSFETs is a critical challenge that must be addressed.