4F<sup>2</sup> DRAM Integration with Vertical Gate (VG) Cell Transistor and Peri-Under-Cell (PUC) Architecture
Process integration of 4F<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> DRAM array with peri-under-cell (PUC) architecture has been successfully demonstrated for the first time, employing vertical gate (VG) cell transistor and wafer bonding process. Fusion wafer bonding and inter-wafer contact techniques enabled wafer-to-wafer integration to provide robust electrical connections between cell and peripheral circuit wafers. Compared to conventional 2D DRAM, superior control over threshold voltage is achieved from back gate bias in VG cell transistor. Precise junction engineering by thermal annealing optimizes cell transistor performance.
Authors
- Seungbum Kim (ORCID: https://orcid.org/0000-0001-8474-6536)
- Shaowei Chu (ORCID: https://orcid.org/0000-0001-5520-296X)
- Sein Kwon
- Seiyon Kim
- Daeik Kim
- Minchul Sung
- J.J. Lee
- Jung Sang Cho (ORCID: https://orcid.org/0000-0001-5584-1526)
- Ju Hyun Myung
- Youngmann Cho
- Seonyong Cha (ORCID: https://orcid.org/0000-0002-9957-8931)
- Jiho Kang (ORCID: https://orcid.org/0009-0006-7922-9263)
- Joodong Park (ORCID: https://orcid.org/0000-0002-0594-0830)
- Jiwoo Kim (ORCID: https://orcid.org/0009-0008-7462-8593)
- Chang-Suk Hyun
- Ildo Kim
- Sunghoon Lee (ORCID: https://orcid.org/0000-0002-3592-388X)
- Kyunghoon Kim (ORCID: https://orcid.org/0000-0003-4316-9327)
- Seung-Cheol Lee (ORCID: https://orcid.org/0000-0001-8995-7463)
- Jun‐Hwe Cha
- Junha Song (ORCID: https://orcid.org/0000-0003-2424-6198)
- Suock Chung
- S.S. Kim
Institutions
- SK Group (South Korea) (KR)
Publication Details
- Published
- 2025-06-08
- DOI
- https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075066
- Citations
- 1
- Primary Topic
- Semiconductor materials and devices
- Type
- article
- Field-Weighted Citation Impact
- 0.73