A 1.7 pJ/bit 10 MHz Calibration-Free PVT Variation and Mismatch Tolerant Latch-Based True Random Number Generator in 4 nm FinFET

This paper presents a calibration-free, latch-based true random number generator (TRNG). The entropy source, a ring structure formed with two inverters and two capacitors connected in series, systematically cancels the offset caused by device mismatches and parasitic capacitances while amplifying the device noise. By combining four entropy sources with XOR operations, the proposed TRNG achieves qualified randomness without additional noise or calibration. The proposed TRNG, fabricated in a core area of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1679 \mu \mathrm{m}^{2}$</tex> using a 4 nm FinFET process, demonstrates robust operation across 80 samples, covering standard process corners(SS, TT, FF) and a wide supply (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.75 \mathrm{V}-0.95 \mathrm{V}$</tex>) and temperature (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$-40^{\circ} \mathrm{C}$</tex> to 85° C) range. Validations on NIST SP 800-22 and NIST SP <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$800-90 \mathrm{B}$</tex> while supply noise of up to 200 mV is being injected highlight its robustness against external perturbations. The TRNG, with an energy efficiency of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1.7 \text{pJ} /$</tex> bit at 0.75 V, reveals its suitability for low-power applications.