A PVT-Robust $\text{16GS}/\mathrm{s} 4 \times \text{TI}$ Time-Domain ADC with Vernier-Based Multipath Flash TDC Achieving $25.7 \text{fJ} / \mathrm{c}-\mathrm{s}$ FoM in 28nm CMOS

A 4-way 16GS/s two-step time-domain ADC with Vernierbased multipath Flash TDC architecture is reported. Benefiting from the proposed Vernier-based Multipath <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{T}_{\text {LSB }}$</tex> Generator (VMTG) and the inherently tracking delay cells, this design achieves PVT robustness for time step ratios and gain between the two stages. Fabricated in 28 nm CMOS, this ADC achieves 35.3 dB SNDR and 51.2 dB SFDR with a Nyquist input at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$16 \text{GS} / \mathrm{s}$</tex> and it consumes 19.6 mW power, leading to a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$25.7 \text{fJ} /$</tex> conv.-step Walden FoM.