An 11.9-ENOB 560-MS/s Subranging ADC Employing Amplifier-Switching Architecture with Multi-Threshold Comparators

This paper proposes a 14-bit 560-MS/s ADC, which employs an amplifier-switching subranging architecture. The proposed architecture enables both high-speed and high-resolution without requiring accurate amplifiers. A multi-threshold comparator with time-latch stages is proposed to achieve 16-level decisions with a single input pair, which reduces its input-referred noise with low power consumption. Fabricated in 28nm CMOS, this work achieves 72.14 dB SNDR at Nyquist input and consumes 9.76 mW at 560 MS/s, which leads to 176.7 dB Schreier FoM.