Analog Cells and Their DTCO Impact on Advanced Node CMOS Analog/Mixed-Signal Circuits

Analog Cells are selected size transistors with optimized cell heights, easy abuttable placement, and pre-drawn structured layouts. Analog Cell Design and Technology Co-Optimization (DTCO) achieves better Performance/Power/Area (PPA) with ~10% analog IP area shrinkage and ~50% layout effort reduction. We also provide an Analog ECO Cell (AEC) flow to enable efficient circuit revision by changing only backend metal layers to reduce turnaround time and mask cost. Based on analog cell-to-cell mapping for both schematic and layout, it also enables easy node-to-node migration through the Analog Design Migration (ADM) flow with 2X productivity enhancement. TSMC introduced silicon-proven analog cells in 2018 at the N5 node, now offered in all advanced finFET (N16 to N3) and new nanosheet nodes with successful customer adoption.