Assessment on Nanosheet Transistor Variants Beyond 2nm Node

Nanosheet (NSH) transistor benefits from its gate-all-around nature and the freedom to reduce channel thickness without pattern collapse as in FinFET to achieve the required SCE for <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{L}_{\mathrm{g}}$</tex> scaling. The possibility of stacking extra channel layers to increase effective channel width and the improved immunity to gate extension effect provide NSH and its variant forksheet (FSH) with a distinct advantage in aggressive cell height <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\text{CH})$</tex> scaling. NSH is thus the next architecture adopted before complementary field-effect transistor (CFET) is ready. This paper explores the issues encountered in CH scaling and potential integration strategies to advance NSH and FSH beyond 2 nm node.

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Published
2025-06-08
DOI
https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075146
Citations
1
Primary Topic
Advancements in Semiconductor Devices and Circuit Design
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article
Field-Weighted Citation Impact
0.73
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article

Assessment on Nanosheet Transistor Variants Beyond 2nm Node

C.H. Hsieh, C.P. Tsao, C.T. Li, K.S. Chen et al.
1 citations
Advancements in Semiconductor Devices and Circuit Design
0.73
article

Assessment on Nanosheet Transistor Variants Beyond 2nm Node

C.H. Hsieh, C.P. Tsao, C.T. Li, K.S. Chen, TL Lee, Chih‐Hao Chang, Y.H. Chen, Perng‐Chih Shen, Vincent S. Chang, Y.H. Tseng, R. Chen, C.Y. Chen, Chi On Chui, Y. Ku, P.N. Chen, Jui‐Han Lu, Bang-Li Wu, C.J. Lin, K. B. Huang, Fenghuan Su, M.C. Chang, S. M. Jang, J.A. Ng, K.T. Lai, S.Y. Wu, Chao‐Chiun Liang, C.C. Chen, Tzu-Jie Lin
article en
1 citations

Abstract

Nanosheet (NSH) transistor benefits from its gate-all-around nature and the freedom to reduce channel thickness without pattern collapse as in FinFET to achieve the required SCE for <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{L}_{\mathrm{g}}$</tex> scaling. The possibility of stacking extra channel layers to increase effective channel width and the improved immunity to gate extension effect provide NSH and its variant forksheet (FSH) with a distinct advantage in aggressive cell height <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\text{CH})$</tex> scaling. NSH is thus the next architecture adopted before complementary field-effect transistor (CFET) is ready. This paper explores the issues encountered in CH scaling and potential integration strategies to advance NSH and FSH beyond 2 nm node.

Taiwan Semiconductor Manufacturing Company (Taiwan) (TW)
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Openalex Percentile: Top 25%
Advancements in Semiconductor Devices and Circuit Design
0.73
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