A 0.5-0.8V 10-85 MS/s 12-Bit SAR ADC in 22nm FDSOI Utilizing an Inverter-Based Comparator Architecture

A low-noise high-speed inverter-based comparator architecture integrated within a SAR ADC is proposed, enabling the ADC to operate down to 0.5 V supply at a state-of-the-art Nyquist rate of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$10 \text{MS} / \mathrm{s}$</tex>, while still achieving 9.5 ENOB and a Walden FoM of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2.0 \text{fJ} /$</tex> conv - step. At its typical supply of 0.8 V, the ADC demonstrates 9.9 ENOB at a Nyquist rate of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$85 \text{MS} / \mathrm{s}$</tex>, with a Walden FoM of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$3.6 \text{fJ} /$</tex> conv-step.