A Novel Backside Signal Inter/Intra-Cell Routing Method Beyond Backside Power for Angstrom Nodes

For the first time, we investigate a power-performancearea (PPA) benefit of novel backside (BS) signal (BSS) routing using BS gate/source-drain contact targeting the Angstrom node. INVx1 with BS-pin has a smaller miller capacitance (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{C}_{\text{miller }}$</tex>) and shows <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$3.0 \sim 3.3 {\%}$</tex> higher ring oscillator (RO) frequency at isopower by BSS inter-cell routing. Even without BS-pin, standard cells can improve frontside (FS) routing congestion and an energydelay product (EDP) by using BSS intra-cell routing. BSS intracell routing based chip has a larger IR drop, but it is mitigated when the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu\text{Bump}$</tex> pitch is small. The BSS intra-cell routing based chip shows an <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$8.61 \sim 9.46 {\%}$</tex> lower power delay product (PDP).