Backside Power Delivery for Power Switched Designs in 2nm CMOS: IR Drop and Block-Level Power-Performance-Area Benefits

We evaluate block-level power-performance-area benefits of backside power delivery networks (BSPDNs) in power switched designs, using Through Silicon Via in the Middle of Line (TSVM) in an N2 (2nm) nanosheet technology. We use an industrial processor design, representative of mobile computing, to compare the BSPDN implementations to traditional frontside power delivery networks (FSPDNs), in both always-on and power switched implementations. BSPDNs benefit both domains, reducing IR drop and enabling smaller block-level area at iso-performance conditions. FSPDNs consume significant routing resources to ensure an acceptable IR drop, especially in power switched designs employing local PDN assists to achieve the target IR drop. Moving PDN to the backside frees up resources, resulting in smaller area for both power switched (-14%) and always-on (17%) domains. BSPDN enables the use of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2 \times$</tex> fewer power switches, achieving an additional 9% area reduction.