Unified Physics-Based CFET Thermal SPICE Considering BEOL, Substrate, and BSPDN Using Adiabatic Cones

For the first time, we present the physics-based thermal SPICE of the split-gate complementary FET (CFET). The passage of heat forms the cone/column-shaped adiabatic surfaces from the transistor level to BEOL and the backside, where can be power delivery network (BSPDN) or substrate. The temperature (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta\mathrm{T}$</tex> relative to the heat sink) of CFET is 2.2 times higher than the non-stacked nanosheet (NS). n-on-p CFET can alleviate temperature by 2°C compared to p-on-n CFET due to the higher thermal resistance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{R}_{\text{th}})$</tex> of SiGe:B S/D than Si:P S/D. The same physical model is used for each level (devices, BEOL, substrate, and BSPDN) and is represented by Cauer ladders.