A 2Nm Gate-All-Around 128Kb Anti-Fuse One-Time Programmable Memory Featuring Dynamic Bit-Line and Sense-Amplifier Offset Cancellation

Decreasing read sensing margin in non-volatile memory (NVM) has become a major challenge in the advanced nodes due to the device down-scaling, lower VDD, and higher gate leakage. We propose a dynamic bit-line (BL) and sense amplifier (SA) offset cancellation read scheme for an anti-fuse one-time programmable (OTP) memory with canceling both offset simultaneously to increase read sensing margin. We fabricated a CMOS logic-compatible 2 nm gate-all-around (GAA) process, 128 Kb anti-fuse OTP for the first time and is silicon-proved with 100 % yield.