PPA Scaling of Flip FET Technology Down to A2 Node Enabled by Architecture Innovations: Self-Aligned Gate, 2T Design with Embedded Power Rail and Ultra-Stacked 4-Tier Transistors

In this work, we carried out a critical examination of Flip FET (FFET) technology from process innovation to circuit design for nodes from A14 to A2. The Fully-aligned FFET (F3ET) featuring self-aligned (SA) FS and BS gates was experimentally demonstrated, with common gate (CG) & split gate (SG) on fins and multi-stack Nanosheets. The Forksheet-based F3ET (F4ET) with embedded Power Rail (ePR) was proposed to reduce the cell height (CH) to 2T. With ultra-stacked 4-tier transistors, the Complementary FET (CFET) based FFET (CFFET) shows further area scaling potential. Comprehensive Power-Performance-Area (PPA) evaluation was conducted on both circuit- and block-level. DTCO knobs were also carefully studied on the A7 F3ET <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">${}_{\text{NS}}$</tex> and A5 F4ET and improved the RO frequency (HP) by 11.3 % and 6.2 % at iso-leakage respectively. A3 HP F4ET outperforms A14 HP Fin-based FFET (FFET <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">${}_{\text{Fin}}$</tex>) by 38.9% at iso-power @ <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{dd}}=0.7 \mathrm{V}. \mathrm{P}$</tex> R results on 32-bit RISC-V cores shows 44.9% (HP) / 49.8% (HD) area scaling and 20.0 % (HP) / 27.9% (HD) frequency improvement from A14 to A5. SRAM scaling down to A2 was also studied in a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$256 \times 256$</tex> array.