NanoStack Transistor Architecture for CMOS 7A Node and Beyond
NanoStack is a sequential stacking CMOS transistor architecture featuring flexible placement of top and bottom nanosheet channels, thermally stable bottom FET gate stack, thin dielectric bonding and more. We project NanoStack with 4-track base cells to deliver <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\sim$</tex> 50% area scaling, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\sim$</tex> 50% iso-power performance improvement or <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\sim$</tex> 70% iso-performance power reduction with respect to the 2nm node, fulfilling fundamental requirements for a competitive multi-node CMOS architecture beyond nanosheet. We demonstrate here for the first time a manufacturable sequential integration of multi-channel nanosheet-on-nanosheet NanoStack CMOS featuring ultra-scaled vertical inter-FET isolation.
Authors
- Yasir Sulehria (ORCID: https://orcid.org/0009-0007-2241-529X)
- S. Reboh (ORCID: https://orcid.org/0000-0001-9331-6327)
- W. K. Li (ORCID: https://orcid.org/0009-0004-3382-3246)
- Nicholas A. Lanzillo (ORCID: https://orcid.org/0000-0003-1205-7402)
- Erin Stuckert
- D. Canaperi
- Rahul Ramachandran (ORCID: https://orcid.org/0000-0002-0647-1941)
- G. Shahidi
- S. Mochizuki
- R. Pujari (ORCID: https://orcid.org/0000-0002-0050-7050)
- J. Strane
- Matthew Malley
- Utkarsh Bajpai (ORCID: https://orcid.org/0000-0002-1974-0450)
- Chen Zhang (ORCID: https://orcid.org/0000-0001-8222-4566)
- T. Standaert
- Takashi Ando (ORCID: https://orcid.org/0000-0002-1097-818X)
- Mohsen Nasseri (ORCID: https://orcid.org/0000-0002-7584-7631)
- Eric R. Miller (ORCID: https://orcid.org/0009-0003-3584-4254)
- Michael Belyansky
- John S. Satterlee (ORCID: https://orcid.org/0000-0002-3396-1014)
- J.C. Tolbert
- Richard Johnson (ORCID: https://orcid.org/0000-0002-4663-7379)
- Spyridon Skordas
- J. Li
- Yu Zhu (ORCID: https://orcid.org/0000-0001-7747-662X)
- T. Yamashita
- Vijay Narayanan (ORCID: https://orcid.org/0009-0008-8433-963X)
- Dechao Guo (ORCID: https://orcid.org/0000-0003-1727-0798)
- Jingyang Zhang (ORCID: https://orcid.org/0000-0002-4347-9416)
- J. Wang
- Nicholas H. Putnam (ORCID: https://orcid.org/0000-0002-1315-782X)
- H. Zhou (ORCID: https://orcid.org/0000-0002-9153-3675)
- B. Peethala (ORCID: https://orcid.org/0000-0001-6221-5929)
- Luciana Meli
- M. Sankarapandian
- Soon‐Cheon Seo
- Jean Wynne
- Wei‐Tsu Tseng (ORCID: https://orcid.org/0000-0002-3941-6009)
- M. Sherony
- L. Tierney
- Dongwoo Sohn (ORCID: https://orcid.org/0000-0002-2476-5548)
- Nirmaan Shanker (ORCID: https://orcid.org/0000-0002-4102-9665)
- D. Durrant
- D. Edelstein
- Mukesh Khare (ORCID: https://orcid.org/0000-0002-5848-2159)
- Emerson K. Cho
- Alex Hubbard
- Ruijie Xie (ORCID: https://orcid.org/0000-0003-2424-1282)
- Shayan Ali Khan (ORCID: https://orcid.org/0000-0002-8880-3793)
- D. Dechene
- John Arnold
- S. Fan
- Albert Chu
- H. Bu
- Nelson Felix
- H. Jagannathan
- Oleg Gluschenkov
- Jim Mazza
- J. Fulham
Institutions
- IBM (United States) (US)
Publication Details
- Published
- 2025-06-08
- DOI
- https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074866
- Citations
- 5
- Primary Topic
- Advancements in Semiconductor Devices and Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 3.65