Exploring FeFET Degradation Mechanisms: Mid-Interlayer as a Viable Solution for Stable Retention, Disturb Immunity, and Low V<sub>th</sub> Variation

This study experimentally investigates the unexplored dynamics of retention loss, disturbance, and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{th}}$</tex> instability in MIFIS FeFETs, featuring a metal-gate interlayer (G.IL)-ferroelectric (FE)-channel interlayer (Ch.IL)-Si stack. To prevent undesired decoupling of polarization <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(P)$</tex> and trapped charges during performance degradation, a mid-interlayer (mid-IL) within the FE layer is proposed. The optimized mid-IL (i) stabilizes the FE phase in the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\overline{\mathrm{H}}\text{fZrO}_{\mathrm{x}}$</tex> (HZO) film, (ii) acts as an energy barrier in the gate stack to suppress trapped charge loss toward the channel, and (iii) mitigates channel percolation issues caused by the polymorphic and polycrystalline nature of FE films. These improvements enable an advanced gate stack design with reduced operation voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(V_{\text{PGM}}/V_{\text{ERS}}:17/$</tex> - 14 V), a wide memory window (MW: 10.5 V), stable TLC retention (F <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta \text{MW}\sim-6$</tex> % after 10 years at 85°C), disturb immunity <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\Delta V_{\text{th}}=0$</tex> after 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> cycles at 12 V), and low <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{\text{th}}$</tex> variation (54% <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta V_{i\mathrm{h}}$</tex> reduction).

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Published
2025-06-08
DOI
https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075182
Citations
3
Primary Topic
Ferroelectric and Negative Capacitance Devices
Type
article
Field-Weighted Citation Impact
2.19

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article

Exploring FeFET Degradation Mechanisms: Mid-Interlayer as a Viable Solution for Stable Retention, Disturb Immunity, and Low Vth Variation

Hyojun Choi, S.S. Park, Jinho Ahn, Daewon Ha et al.
3 citations
Ferroelectric and Negative Capacitance Devices
2.19
article

Exploring FeFET Degradation Mechanisms: Mid-Interlayer as a Viable Solution for Stable Retention, Disturb Immunity, and Low Vth Variation

Hyojun Choi, S.S. Park, Jinho Ahn, Daewon Ha, Giuk Kim, Wanki Kim, Hoon Kim, Sangho Lee, Kwangsoo Kim, Sanghun Jeon, Kwangyou Seo, Seokjoong Shin
article en
3 citations

Abstract

This study experimentally investigates the unexplored dynamics of retention loss, disturbance, and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{th}}$</tex> instability in MIFIS FeFETs, featuring a metal-gate interlayer (G.IL)-ferroelectric (FE)-channel interlayer (Ch.IL)-Si stack. To prevent undesired decoupling of polarization <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(P)$</tex> and trapped charges during performance degradation, a mid-interlayer (mid-IL) within the FE layer is proposed. The optimized mid-IL (i) stabilizes the FE phase in the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\overline{\mathrm{H}}\text{fZrO}_{\mathrm{x}}$</tex> (HZO) film, (ii) acts as an energy barrier in the gate stack to suppress trapped charge loss toward the channel, and (iii) mitigates channel percolation issues caused by the polymorphic and polycrystalline nature of FE films. These improvements enable an advanced gate stack design with reduced operation voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(V_{\text{PGM}}/V_{\text{ERS}}:17/$</tex> - 14 V), a wide memory window (MW: 10.5 V), stable TLC retention (F <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta \text{MW}\sim-6$</tex> % after 10 years at 85°C), disturb immunity <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\Delta V_{\text{th}}=0$</tex> after 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> cycles at 12 V), and low <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{\text{th}}$</tex> variation (54% <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta V_{i\mathrm{h}}$</tex> reduction).

Korea Advanced Institute of Science and Technology (KR), Samsung (South Korea) (KR), Hanyang University (KR)
Neurosciences Research Foundation, Samsung
Openalex Percentile: Top 11%
Ferroelectric and Negative Capacitance Devices
2.19
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