First Demonstration of 2-floor GAA In₂O₃ Nanosheet FET Enabled by TiN Sacrificial Layers and Fluorine Passivation

The true two-floor stacked PEALD (plasma-enhanced atomic layer deposition) In<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>O<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> gate-all-around (GAA) nanosheet (NS) FET is demonstrated for the first time by the novel metallic sacrificial layers (MSLs, TiN). MSLs connect stacked S/D and form n<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> region to improve contact resistance. Channel release by SF<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</inf> can shift <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\mathrm{T}}$</tex> positively by passivating oxygen vacancy (Vo) defects. The gate stack is deposited all at once by ALD to realize the GAA structure. The process temperatures are below 300°C with the back-end-of-line (BEOL) compatibility. The two-floor GAA NSFET achieve high drive current <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{I}_{\text{on}})$</tex> of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$146\mu \mathrm{A}/\mu \mathrm{m} {@} \mathrm{V}_{\text{OV}}=\mathrm{V}_{\text{DS}}=1\mathrm{V},\ \mathrm{I}_{\text{on}}/\mathrm{I}_{\text{off}} &gt; 10^{7}$</tex>, and high stability of positive bias stress (PBS) with the V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> shift as small as 60mV at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{OV}}=3.6\mathrm{V}$</tex> for 1000sec. Furthermore, adding IGZO into In<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>O<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> channels achieves a positive V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> of 1.6V with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{I}_{\text{on}}$</tex> of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$77\mu \mathrm{A}/\mu \mathrm{m}$</tex> at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{OV}}=\mathrm{V}_{\text{DS}}=1\mathrm{V}$</tex>. The stacked NS architecture enables oxide semiconductor (OS) FETs to overcome <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{I}_{\text{on}}$</tex> limitations due to low mobility.