A Fractional-N Digital-PLL Based on a Power-Gated Ring-Oscillator and a Frequency-Stabilizing Loop Achieving 74fs Jitter Under $3 \text{mV}_{\text{pp}}$ Supply Ripple

A 10 GHz fractional-N digital PLL with a power-gated ring-oscillator (PGRO) to reduce digital-to-time converter (DTC) range and a PGRO-frequency-stabilizing loop to mitigate supply sensitivity is presented. The PLL achieves 74 fs and 81 fs rms jitter, when a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$3 \text{mV}_{\text{pp}}$</tex> sinusoid and a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2.5 \text{mV}_{\text{rms}}$</tex> white noise are superimposed to the PGRO supply, respectively.