First Demonstration of Monolithic 3-Tier Nanosheet Transistor Stacking with Split Gate Featuring Tri-State Inverter/Half Sram Functionalities
Monolithic three-tier transistor stackings with GeSi nanosheets, split gate, and multiple pn layer isolation are demonstrated for the first time. The split-gate process enables one common-gate CFET and one nFET underneath to achieve 6T STAM design with 3T footprint. The functionalities of tristate inverters and half-SRAM (1PD/1PU/1PG) of monolithic three-tier transistor stacking are successfully demonstrated.
Authors
- Yi Huang (ORCID: https://orcid.org/0000-0002-0597-0140)
- Tsung-Han Tsai (ORCID: https://orcid.org/0000-0002-2306-2269)
- Wei-Jen Chen (ORCID: https://orcid.org/0000-0003-1748-7743)
- Bo‐Wei Huang (ORCID: https://orcid.org/0000-0002-1405-8639)
- C. W. Liu (ORCID: https://orcid.org/0000-0002-6439-8754)
- Xin-Yuan Lin
- Yingqi Liu (ORCID: https://orcid.org/0000-0003-1249-8929)
- Chun-Yi Cheng (ORCID: https://orcid.org/0000-0002-8570-3789)
- Chih‐Hsuan Lu
- Min-Kuan Lin
- Ching-Wang Yao
- Ding-Wei Lin
Institutions
- National Taiwan University (TW)
Publication Details
- Published
- 2025-06-08
- DOI
- https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074914
- Citations
- 2
- Primary Topic
- Semiconductor materials and devices
- Type
- article
- Field-Weighted Citation Impact
- 1.46