A 7-Bit 150-GSa/s DAC in 5nm FinFET CMOS
We present a 7-bit wireline source-series terminated (SST) digital-to-analog converter (DAC) in 5nm FinFET CMOS. The number of unit cells is reduced by employing SST cells with relative weight 1 and 4. From an eight-phase clock, each unit cell creates clock pulses which are in turn used to control the three-stage 8: 1 multiplexer. At 150 GSa/s, the ENOB was measured to be 4.1bit for a 72.8GHz sinewave. The DAC consumes 621mW from a 0.9V and 0.96V supply. Eye diagrams of 150Gbit/s non-return to zero modulation and 300Gb/s P AM-4 are measured, pre-equalized using a 10-tap feedforward equalizer.
Authors
- Ewout Martens (ORCID: https://orcid.org/0000-0001-5485-1837)
- Bart Moeneclaey (ORCID: https://orcid.org/0000-0002-9444-6235)
- Angelo Parisi (ORCID: https://orcid.org/0000-0003-1397-9011)
- Joris Lambrecht (ORCID: https://orcid.org/0000-0001-8291-0339)
- Gertjan Coudyzer (ORCID: https://orcid.org/0000-0002-3915-394X)
- Jan Craninckx (ORCID: https://orcid.org/0000-0002-3980-0203)
- Joris Van Kerrebrouck
- Anirudh Kankuppe (ORCID: https://orcid.org/0000-0002-0114-1193)
- Peter Ossieur (ORCID: https://orcid.org/0000-0002-8737-9142)
Institutions
- Ghent University Hospital (BE)
- Ghent University (BE)
- iMinds (BE)
- IMEC (BE)
Publication Details
- Published
- 2025-06-08
- DOI
- https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075168
- Citations
- 2
- Primary Topic
- Advancements in Semiconductor Devices and Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 1.46
Funders
- Taiwan Semiconductor Manufacturing Company