Backside Routing Enablement Considerations for Advanced Node GAA Devices
Backside routing is an innovative feature offered by several foundries in Gate-All-Around (GAA) nodes at 3nm and beyond. In this paper, we will discuss the considerations for digital design implementation to use the backside layers most efficiently for maximizing PPA (Power Performance Area). The considerations involve choosing the right strategies for technology definition and implementation flow for power, clock and specific signals that can benefit from backside routing.
Authors
- Anisur Rahman (ORCID: https://orcid.org/0000-0003-2346-4484)
- K. Subramani (ORCID: https://orcid.org/0000-0001-5821-5117)
- Dan J. Dechene
- Albert Chu
- Rwik Sengupta
- Matthew Loden
Institutions
- IBM (United States) (US)
- Cadence Design Systems (United States) (US)
Publication Details
- Published
- 2025-06-08
- DOI
- https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074879
- Primary Topic
- Energy Harvesting in Wireless Networks
- Type
- article
- Field-Weighted Citation Impact
- 0.00