A 58.9fs-Jitter Fractional-N Digital PLL Using a Double-Edge Variable-Slope DTC
This work presents a fractional-N digital PLL achieving low-jitter by leveraging the combination of a XOR frequencydoubler and a power-efficient double-edge variable-slope digital-to-time converter (DTC). The prototype demonstrates 58.9fs jitter and -61.8 dBc fractional spur at 9.25 GHz, with 18.3 mW power and 125 MHz input reference frequency.
Authors
- Marco Rossoni (ORCID: https://orcid.org/0000-0003-2714-9043)
- Simone M. Dartizio (ORCID: https://orcid.org/0000-0001-5983-5609)
- Francesco Tesolin (ORCID: https://orcid.org/0000-0002-9743-5726)
- Silvia Gallucci (ORCID: https://orcid.org/0009-0000-0481-1554)
- Andrea L. Lacaita (ORCID: https://orcid.org/0000-0003-0315-514X)
- Giacomo Castoro (ORCID: https://orcid.org/0000-0002-8963-1575)
- Salvatore Levantino (ORCID: https://orcid.org/0000-0003-0895-1700)
- Pietro Salvi (ORCID: https://orcid.org/0009-0007-4707-6669)
- Riccardo Moleri
- D. Lodi Rizzini
- D. Fagotti
- G. R. Trotta
Institutions
- Politecnico di Milano (IT)
Publication Details
- Published
- 2025-06-08
- DOI
- https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075214
- Primary Topic
- Advancements in PLL and VCO Technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.00