A Calibration-Free Adpll with < -80 dBc Fractional Spur Based on Pseudo-Random Phase Modulation

This work presented a fractional-N digital PLL that leveraged pseudo-random phase modulation and demodulation technique to mitigate fractional spurs. By decoupling the periodicity of control words from the non-linearity of the digital phase interpolator (DPI), the fractional spurs induced by DPI non-linearity were effectively suppressed. The digital PLL fabricated in 40nm CMOS, demonstrated fractional spurs below noise floor at near-integer channels.