Uncovering True DIBL in Oxide-Semiconductor FETs: Impact of Negative Bias Stress and its Significance in 2T0C DRAM Retention

In this study, we demonstrate the majority of drain-induced barrier lowering (DIBL) effects observed in BEOL-compatible oxide semiconductor FETs (OSFETs) may not represent the true DIBL phenomenon. For the first time, we reveal that these effects are instead caused by the negative threshold voltage shift <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\Delta V_{\text{TH}})$</tex> induced by negative bias stress (NBS) during gate voltage sweeping. This insight helps explain the discrepancy between experimental and theoretical retention in OSFET -based DRAMs. Our findings are further substantiated by a significant improvement in retention performance for OSFET -based 2T0C DRAM at 77 K, where both DIBL and the NBS-induced <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta V_{\text{TH}}$</tex> are suppressed. Additionally, for a 2T0C DRAM using OSFETs with a channel length <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(L_{\text{CH}})$</tex> of 80 nm, negligible data loss was observed after 1000 seconds of data holding.