High-Performance Monolithic 3D CMOS Enabled by Orientation-Aligned Seedless Laser Crystallization and Ultra-Shallow Laser Activation

In this study, we demonstrate PSLC Si-based CMOS devices on the M3D top layer using a seedless crystallization process. Laser crystallization forms single-orientation Si channels (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$25\ \mu \mathrm{m}$</tex> grain size), enhancing carrier mobility. Laser S/D activation achieves low contact resistivity <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\sim 10^{-8} \Omega\cdot \text{cm}^{2})$</tex> below 400 °C, meeting M3D constraints. PSLC-Si CMOS devices exhibit <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{I}_{\text{ON}}/\mathrm{I}_{\text{OFF}} &gt; 10^{8}$</tex> with high <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu_{\text{FE},\mathrm{e}}(521 \text{cm}^{2}/\mathrm{V}\cdot \mathrm{s})$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu_{\text{FE},\mathrm{h}}(163\ \text{cm}^{2}/\mathrm{V}\cdot \mathrm{s})$</tex>. CMOS inverters show clear switching transitions, confirming feasibility for M3D logic applications. These results validate the potential of a fully laser-based process for M3D-integrated logic devices. Keyword: Monolithic 3D (M3D), Patterned Seedless Laser-Crystallization (PSLC), Si, Laser activation, Mobility