A 4.2 Gb/S $5^{\text {th }}$ Generation F-Chip of Toggle 5.1 Specification With All-Path Speed Boosting Scheme and Sca Protocol for High Density Nand Flash Applications

This paper introduces a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4.2 ~\text{Gb} / \mathrm{s} 5^{\text {th }}$</tex> generation F-chip operating at a 1.1 V supply voltage. To achieve high-speed performance even in high-capacity memory packages, a speed boosting scheme is proposed to ensure optimal write and read performance. This scheme includes technologies for correcting the duty cycle, offset and skew of DQ and DQS signals. To mitigate leakage in the devices, a power gating technique with whole of chip is also introduced. Also, a SCA converter design is presented to overcome command speed bottlenecks for improvement of I/O efficiency. This proposed work achieves a 37 % reduction in energy/bit, with a 1.4 x speed improvement, and a 92 % reduction in standby current through power gating.

Authors

Institutions

Publication Details

Published
2025-06-08
DOI
https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074954
Primary Topic
Semiconductor Lasers and Optical Devices
Type
article
Field-Weighted Citation Impact
0.00
Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

A 4.2 Gb/S $5^{\text {th }}$ Generation F-Chip of Toggle 5.1 Specification With All-Path Speed Boosting Scheme and Sca Protocol for High Density Nand Flash Applications

Jichull Jeong, Eunsang Lee, Jung-June Park, Mingyu Lee et al.
Semiconductor Lasers and Optical Devices
article

A 4.2 Gb/S $5^{\text {th }}$ Generation F-Chip of Toggle 5.1 Specification With All-Path Speed Boosting Scheme and Sca Protocol for High Density Nand Flash Applications

Jichull Jeong, Eunsang Lee, Jung-June Park, Mingyu Lee, G. Cha, Jun‐Ho Boo, Doobock Lee, Sung-Chul Go, Soomin Ko, Hwaseok Oh, Kyeonghwan Park, Chi-Weon Yoon, Soon-Jae Won, Seung‐Wan Kang, I.S. Cho, Seong-Hoon Kang, Seung-Jin Park, Young‐Min Kim, Seunghoon Lee, Minjae Lee, Yongmin Kim, Young-Min Kang, Yongjin Kim, Jisun Lee, Ki-Sung Kim, Youngmin Jo, Myoungbo Kwak, Eung Suk Lee, Moon-Ki Jung
article en

Abstract

This paper introduces a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4.2 ~\text{Gb} / \mathrm{s} 5^{\text {th }}$</tex> generation F-chip operating at a 1.1 V supply voltage. To achieve high-speed performance even in high-capacity memory packages, a speed boosting scheme is proposed to ensure optimal write and read performance. This scheme includes technologies for correcting the duty cycle, offset and skew of DQ and DQS signals. To mitigate leakage in the devices, a power gating technique with whole of chip is also introduced. Also, a SCA converter design is presented to overcome command speed bottlenecks for improvement of I/O efficiency. This proposed work achieves a 37 % reduction in energy/bit, with a 1.4 x speed improvement, and a 92 % reduction in standby current through power gating.

Samsung (South Korea) (KR), Samsung Pharm (South Korea) (KR)
Affordable and clean energy
Openalex Percentile: Top 82%
Semiconductor Lasers and Optical Devices
DOISourceOpenAlex
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.