A 77 fJ/Bit 8 Gbps Low-Latency Self-Timed Die-to-Die Link for 2.5D and 3D Interconnect in 3nm

This work presents a self-timed die-to-die link that serializes 4 data bits per pin for 2.5D or 3D interconnects using a standard adaptive digital clock and voltage supply. The link achieves 8 Gbps of per-pin bandwidth with a latency of 1 cycle, energy efficiency of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$77 \text{fJ} / \mathrm{b}$</tex>, and bandwidth density of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$44 \text{Tbps} / \text{mm}^{2}$</tex> at 0.7 V. The link was implemented on a testchip as side-by-side transmitter and receiver macros connected with on-chip wires in a 3 nm process.