A 0.71nJ, 1.53GS/s Throughput 256-FFT Using Floating Point Analog Computation

We propose a 256-point FFT engine using the first analog floating point implementation. The proposed method encodes the mantissa value with both voltage and pulse width and a digital 4-bit exponent. It features automatic calibration to cancel process variation and attains precision and dynamic range equivalent to 12.3 bit digital fixed point. Implemented in 22 nm CMOS, the chip demonstrates the first reported sub-nJ energy/FFT (0.71 nJ) at a high throughput of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1.53 \text{GS} / \mathrm{s}$</tex>.