Floating Point Cordic Processor in Hyperbolic Coordinate System
This paper presents the implementation of single-precision and double-precision floating-point square root, exponential, and natural logarithm functions with the Cordic algorithm. The Cordic processor is interfaced with the floating-point unit of an IEEE 1754 ISA compliant 32-bit processor. The hardware is validated by comparing the results with the Intel and SPARC PCs.
Authors
- Nimmy Joseph
- K Padmakumar
- Joji Daniel
- L Jayalekshmi
Institutions
- Indian Space Research Organisation (IN)
- Vikram Sarabhai Space Centre (IN)
Publication Details
- Published
- 2025-05-23
- DOI
- https://doi.org/10.1109/iccc64910.2025.11077237
- Primary Topic
- Numerical Methods and Algorithms
- Type
- article
- Field-Weighted Citation Impact
- 0.00