3D Stacked FET (3DSFET) Logic and SRAM Technology Featuring Single Diffusion Break (SDB) and Back Side Interconnect (BSI) at 48 nm CPP for Advanced Mobile and High Performance Computing (HPC) Applications

For the first time, we report experimental demonstration of highly scalable 3D stacked FET (3DSFET) logic with single diffusion break (SDB) and SRAM bit-cell at 48 nm CPP. Key features include nFET gate-all-around multi-bridge channel (GAA MBCFET <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">${ }^{\text {TM }}$</tex>) vertically stacked on pFET GAA MBCFET <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">${ }^{\text{TM}}$</tex> for reducing logic standard cell height by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$&gt;50 \%$</tex>, SDB for reducing logic block area without pitch scaling by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$&gt;10 \%$</tex>, self-aligned direct backside contact (SA-DBC) and back side interconnects (BSI) for power and signal lines with relaxed metal pitch, compared to our 3 nm node. Moreover, it can provide <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$&gt;55 \%$</tex> smaller SRAM bit-cell with read static noise margin (SNMR) & write margin (WRM) of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$180 \&amp; 250 \text{mV}, 60\ \&amp; 50 \text{mV}$</tex> for <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{DD}}=0.7$</tex> and 0.3 V, respectively. At the same time, SRAM bit-cell leakage decreases by 15.4 % at 125° C with unique structural benefits to fully suppress leakage current such as sub-nanosheet, n-p isolation, GIDL and junctions.