First Demonstration of Symmetric Dual-Sided Vertical FET (DSVFET) for Energy Efficient Computing (EEC): From Processes and Devices to Circuits

For the first time, we proposed and demonstrated the symmetric dual-sided vertical FET (DSVFET) experimentally. The DSVFET not only inherits low leakage, drive voltage and parasitic benefits from the standard VFET but also features unique dual-sided S/Ds with smaller footprint and better symmetry, perfectly suiting the energy efficient computing. A series of new processes and DTCO methods were developed to study the device structure, performance and circuit design. DSVFET with aggressive contact gate pitch (CGP) of 50 nm and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{Lg}_{\mathrm{g}}$</tex> of 19 nm was realized. DSVFET was also validated with nearly symmetric behaviors (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta \mathrm{C}_{\text{eff }} \&amp; \Delta$</tex> delay <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$&lt;3 {\%}$</tex>) and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$38 \% / 60 {\%}$</tex> lower power than FinFET for 2 nanosheets (2NS) and 1NS design at iso-frequency based on ring oscillator (RO) simulation respectively. A RISC-V core was used for block level evaluation and 17.4% lower energy, 15% lower energy delay product (EDP) and 39.8% smaller areas were identified for the 1NS DSVFET with PowerVia (PV). DSVFET has proved to be a great candidate for future's EEC.

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Published
2025-06-08
DOI
https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075018
Primary Topic
Advancements in Semiconductor Devices and Circuit Design
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article
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article

First Demonstration of Symmetric Dual-Sided Vertical FET (DSVFET) for Energy Efficient Computing (EEC): From Processes and Devices to Circuits

Min Xu, Wen Bu, Xiang Wu, Lisheng Zhang et al.
1 links
Advancements in Semiconductor Devices and Circuit Design
article

First Demonstration of Symmetric Dual-Sided Vertical FET (DSVFET) for Energy Efficient Computing (EEC): From Processes and Devices to Circuits

Min Xu, Wen Bu, Xiang Wu, Lisheng Zhang, Xin He, Jinfeng Kang, Ru Huang, Ying‐Hao Chu, Tianxi X. Liu, Zhe Xü, Ruoyu Wang, Yue Wu, Zhenhua Wang, Ming Li, Yang Liu, Jian Zhang, Yu Wang, Peng Ren, Yili Zhang, Fengrui Sun, Jinlei Wu, Huiling Lü, Heng Wu, Shuhan Liu, Li Li
article en

Abstract

For the first time, we proposed and demonstrated the symmetric dual-sided vertical FET (DSVFET) experimentally. The DSVFET not only inherits low leakage, drive voltage and parasitic benefits from the standard VFET but also features unique dual-sided S/Ds with smaller footprint and better symmetry, perfectly suiting the energy efficient computing. A series of new processes and DTCO methods were developed to study the device structure, performance and circuit design. DSVFET with aggressive contact gate pitch (CGP) of 50 nm and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{Lg}_{\mathrm{g}}$</tex> of 19 nm was realized. DSVFET was also validated with nearly symmetric behaviors (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta \mathrm{C}_{\text{eff }} \&amp; \Delta$</tex> delay <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$&lt;3 {\%}$</tex>) and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$38 \% / 60 {\%}$</tex> lower power than FinFET for 2 nanosheets (2NS) and 1NS design at iso-frequency based on ring oscillator (RO) simulation respectively. A RISC-V core was used for block level evaluation and 17.4% lower energy, 15% lower energy delay product (EDP) and 39.8% smaller areas were identified for the 1NS DSVFET with PowerVia (PV). DSVFET has proved to be a great candidate for future's EEC.

Peking University (CN), Songshan Lake Materials Laboratory (CN), Fraunhofer Institute for Integrated Circuits (DE), Shanghai Fudan Microelectronics (China) (CN), Shanghai Micro Electronics Equipment (China) (CN)
Affordable and clean energy
Openalex Percentile: Top 82%
Advancements in Semiconductor Devices and Circuit Design
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