A 94.1%-Efficiency Flying-Capacitor-Shared 2-Inductor 3-Level Boost Converter with Simultaneous V_CF and I_L Balance Achieving <0.92%-V_CF and <0.22%-I_L Error

In this paper, a flying-capacitor-shared 2-inductor 3-level boost converter (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$C_{\mathrm{F}}-2 ~\mathrm{L} 3 \text{LV}$</tex>) is presented. A unified imbalance calibration technique (UICT) is proposed to achieve <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{\text {CF }}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$I_{\mathrm{L}}$</tex> balance, simultaneously. The <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$C_{\mathrm{F}}$</tex>-2L3LV with UICT features a wide operating range that are not constrained by duty-cycle (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$D$</tex>) and conversion ratio (CR) limitations, while maintaining the voltage stress on all switches at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.5 V_{\text {o. }}$</tex> The test chip, fabricated using a 180 nm CMOS process, achieves simultaneous <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{\text{CF}}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$I_{\mathrm{L}}$</tex> balancing with balancing errors of less than 0.92% and 0.22%, respectively, under a 0.2Ω resistance mismatch. A peak efficiency was measured at 94.1%.