A 55.8-to-64.2GHz, $58.3\text{fs}_{\text{rms}}$ -Jitter, $-250.2\text{dB-FoM}_{\mathrm{J}}$ Fractional-N Cascaded PLL in 28nm CMOS

We present a V-band fractional-N cascaded PLL achieving the integrated jitter of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$58.3\text{fs}_{\text{rms}}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{FoM}_{\mathrm{J}}$</tex> of-250.2dB. A fully differential voltage domain quantization (Q)-noise cancellation of the 1<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup>-stage reference sampling PLL suppresses the Q-noise of the delta-sigma modulator <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\Delta\Sigma \mathrm{M})$</tex> with <0.92LSB INL and <0.08mV resolution while only consuming 0.62mW. The 2<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup>-stage sub-sampling PLL features a 0.82mW switched capacitor frequency-to-voltage converter-based FLL, addressing a harmonic lock issue without a power-hungry mmWave frequency divider. Its frequency re-acquisition time is within <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.42\mu \mathrm{s}$</tex>.