Vertical 2T-nC FeRAM Demonstration: BEOL Read Transistor for 4F² Memory Strings and Two-Terminal Selector Design for Polarization Disturb Mitigation

In this work, we demonstrate a vertical 2T-nC FeRAM with a back-end-of-line (BEOL) read transistor (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$T_{\mathrm{R}}$</tex>) for <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4 \mathrm{F}^{2}$</tex> string and propose a selector design to mitigate polarization disturb in passive capacitor crossbar arrays. Key contributions include: 1) successful integration and operation composed of a Si MOSFET write transistor (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$T_{\mathrm{W}}$</tex>), 3-layer cylindrical ferroelectric capacitors, and Si-doped <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{In}_{2} \mathrm{O}_{3}$</tex> BEOL <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$T_{\mathrm{R}}$</tex>, demonstrating the feasibility of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4 \mathrm{F}^{2} 2 \mathrm{T}-\text{nC}$</tex> string; 2) introducing nonlinearity into the capacitor stack to suppress ferroelectric voltage drop under inhibition biases while maintaining sufficient write voltage, reducing disturbance; 3)modeling and experimental validation of inserting a metalsemiconductor (a-Si)-metal (MSM) selector into the capacitor in mitigating the disturb, particularly achieving 9x reduction of disturb after <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$10^{6}$</tex> cycles in the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{\mathrm{W}} / 2$</tex> scheme.