A 46GS/s 7-Bit Time-Interleaved Time-Domain ADC with Synthesizable Unit ADCs in 16nm FinFET

A 7-bit 16-way time-interleaved time-domain analog-todigital converter (TDADC) is presented with unit ADCs synthesized using Verilog code and fully-automated standard digital place-and-route techniques. The proposed design introduces capacitor-based distortion compensation in the voltage-to-time converter and employs a novel 3-input time comparator with implicit phase interpolation in the fine time-to-digital converter to reduce power and area. Fabricated in 16 nm FinFET, the proposed ADC operates at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$46 \text{GS} / \mathrm{s}$</tex>, achieves <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$78 \text{fJ} /$</tex> conv.-step at Nyquist, has 20.1 GHz 3 dB input bandwidth, and occupies <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.085 ~\text{mm}^{2}$</tex> area.