BEOL-Compatible ITO FET with Ultra-Short Channel Length of 5 nm

For the first time, a novel drain in-situ shadowing mask (DISM) technique has been proposed for ultra-short channel (USC) transistor fabrication. This technique enables the realization of an ITO FET with the shortest channel length (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$L_{\text{ch}}$</tex>) of 5 nm among all oxide semiconductor (OS) FETs, achieving a record-high maximum transconductance (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$G_{\mathrm{m}, \max }$</tex>) of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1104 \mu ~\mathrm{S} / \mu \mathrm{m}$</tex> among all ITO FETs, and a high maximum drain current (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$I_{\mathrm{D}, \max }$</tex>) of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2061 \mu ~\mathrm{A} / \mu \mathrm{m}$</tex>. The absence of off-state tunneling in such an USC ITO FET has been confirmed via both experimental and simulation results. Furthermore, the 5 nm <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$L_{\text {ch }}$</tex> device performs a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$S S$</tex> as low as <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$34.5 \text{mV} /$</tex> decade at 6 K, disclosing a tiny glimpse into the full potential of cryogenic USC ITO FETs.