A CMOS-Compatible 12nm 8Mb MLC RRAM Enabling Producible 2-Bit Per Cell for High Energy Efficiency Compute-In-Memory in Edge AI Applications

A 12nm 2-bit per cell RRAM, featuring co-optimization across circuit design, write algorithms, and memristor engineering, demonstrates remarkable 10K-cycle endurance and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$85^{\circ} \mathrm{C} / 10 \text{yr}$</tex> retention on physical 8-megabit arrays, exhibiting superior inference accuracy in compute-in-memory applications. Notably, the intrinsic RRAM cells present 1Bcycle endurance and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$125^{\circ} \mathrm{C} / 10 \text{yr}$</tex> retention capability. Achieving this requires precise tuning of the oxygen and vacancy density in the memristor through circuit design and write algorithms, and accounts for the vacancy formationrecombination energy by adjusting memristor property in each storage state. This innovation paves the way for edge artificial intelligence (AI) processors to utilize a simple RRAM solution for firmware storage and high energy efficiency AI computing in application-specific-integrated-circuits (ASIC).