A 3nm FinFET 563kbit 35.5Mbit/mm<sup>2</sup> Dual-Rail SRAM with 3.89pJ/Access High Energy Efficient andμW/Mbit 1-Cycle Latency Low-Leakage Mode
This paper presents a Single-port high-density (HD) 6T SRAM for mobile application. The macro uses eXtended Dual Rail (XDR) architecture and two proposed techniques. The Delaying-Write-WL (DeWL) technique resolves the problem of contention between the cell and the write-driver (WDRV). The 1-cycle latency low-leakage mode (1-CLM) enables to turn off all BL pre-chargers during no operation (NOP). A 3-nm FinFET test chip can achieve the reduction of 17 % in active energy and 10 % in stand-by leakage by these techniques.
Authors
- Kang-Hui Peng
- Koji Nii (ORCID: https://orcid.org/0000-0002-9986-5308)
- Min Zhou (ORCID: https://orcid.org/0000-0002-8718-8506)
- Juan LIU
- Masaya Hamada (ORCID: https://orcid.org/0000-0002-5830-5283)
- Makoto Yabuuchi (ORCID: https://orcid.org/0000-0003-1515-4726)
- Y. Aoyagi (ORCID: https://orcid.org/0009-0000-6406-1601)
- Chien‐Yu Huang (ORCID: https://orcid.org/0000-0001-6341-5471)
- Hung-Jen Liao
- Yuichiro Ishii
- Hong-Chen Cheng
- Yu-Hao Hsu (ORCID: https://orcid.org/0000-0002-3165-1960)
- Tomotaka Tanaka (ORCID: https://orcid.org/0009-0009-0000-227X)
- Isabel Wang
- Kazuto Mizutani
- Tsung-Yung Jonathan Chang (ORCID: https://orcid.org/0009-0007-6505-5474)
Institutions
- Taiwan Semiconductor Manufacturing Company (United States) (US)
- Taiwan Semiconductor Manufacturing Company (Taiwan) (TW)
Publication Details
- Published
- 2025-06-08
- DOI
- https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074969
- Primary Topic
- Advancements in Semiconductor Devices and Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00