A 16NM 550-1320 BTOPS/W NPU Exploiting Training-Free Structured Bit-Level Sparsity and Dynamic Dataflow Processing
To jointly achieve aggressive weight compression as well as high compute utilization for neural and transformer workloads, this chip implements a sparse NN processor exploiting structured bit-level sparsity and dynamic dataflows. Without a need for costly network retraining, the chip achieves an energy efficiency of 550-1320 BTOPS/W, realizing an up to x6.82 efficiency improvement compared to the SotA.
Authors
- Marian Verhelst (ORCID: https://orcid.org/0000-0003-3495-9263)
- Man Shi (ORCID: https://orcid.org/0000-0003-1675-6235)
- Chao Fang (ORCID: https://orcid.org/0000-0003-3430-1189)
- Vikram Jain (ORCID: https://orcid.org/0000-0002-1267-1683)
- Wim Dehaene (ORCID: https://orcid.org/0000-0002-6792-7965)
- Weijie Jiang (ORCID: https://orcid.org/0000-0003-3686-4639)
- Antony Joseph
Institutions
- NXP (Belgium) (BE)
- KU Leuven (BE)
Publication Details
- Published
- 2025-06-08
- DOI
- https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074933
- Primary Topic
- VLSI and Analog Circuit Testing
- Type
- article
- Field-Weighted Citation Impact
- 0.00