Voltage Reduction (1.4V) and Array Scaling (41nm) of Ferroelectric NVDRAM for Low-Power and High-Density Applications
We present a second generation of scaled Ferroelectric NVDRAM [1] with a reduced x- and y-direction pitch (41nm), a thinner ferroelectric stack (5nm) and a lower array operating voltage (Read/Write at 1.4V). We present full chip array data, showing a >250mV window at −4σ after 1E10 cycles. This is the densest 1T1C ferroelectric technology with such high performance. Multiple material and electrical challenges were addressed to ensure performance was maintained at reduced dimensions.
Authors
- M. Mariani
- Matthew Jerry (ORCID: https://orcid.org/0000-0001-7220-1854)
- Sameer Chhajed
- Alessandro Calderoni
- D. P. Ettisserry (ORCID: https://orcid.org/0000-0002-4214-2141)
- Matthew J. Hollander
- Mark H. Fischer (ORCID: https://orcid.org/0000-0003-0810-6064)
- Ashonita Chavan
- Kamal Karda (ORCID: https://orcid.org/0000-0001-6667-1462)
- Nirmal Ramaswamy
- J. Zahurak
- Beth Cook
- D. Mills
- M. Balakrishnan (ORCID: https://orcid.org/0000-0001-9164-3068)
- Albert Liao
Institutions
- Micron (United States) (US)
Publication Details
- Published
- 2025-06-08
- DOI
- https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075050
- Citations
- 3
- Primary Topic
- Ferroelectric and Negative Capacitance Devices
- Type
- article
- Field-Weighted Citation Impact
- 2.19