A 6+ Ghz 128 Kb Multi-Port L1 Cache Using Ground Rule Clean 10T Bitcells in 5Nm Technology
A <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$6+$</tex> GHz multi-port 10T Ground Rule Clean (GRC) compact Cache is implemented in the recently announced IBM Telum II processor [1]. It features a Multi port design (2 Read and 1 Write) with fine grain banked architecture minimizing read and write collisions. The design is functional across various corner conditions without read and write assist circuits.
Authors
- Derek Leu
- Bill Huott
- Steve Kim (ORCID: https://orcid.org/0000-0002-9519-077X)
- P. Bunce
- John D. Davis (ORCID: https://orcid.org/0000-0003-0266-0857)
- Dong‐Ho Lee (ORCID: https://orcid.org/0000-0001-5545-9626)
- Zhiying Chen (ORCID: https://orcid.org/0000-0002-1777-8455)
- Rajiv Joshi (ORCID: https://orcid.org/0009-0007-7486-1531)
- R. L. Hayes
- Juergen Pille
- Uma Srinivasan
- Antonio Pelella
- Gregory Fredeman
- Ismael Cervantes
- Genadi Tverskoy
- Brian Yavoich
Institutions
- Poughkeepsie Public Library District (US)
- IBM (Germany) (DE)
Publication Details
- Published
- 2025-06-08
- DOI
- https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074981
- Primary Topic
- Radio Frequency Integrated Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00