Orthogonal $\mathbf{V}_{\mathbf{T}}$ Tuning for Oxide Semiconductor 2T Gain Cell Enabled by Interface Dipole Engineering

We demonstrate interface engineering (eng.) of the gate dielectric as an independent knob to tune the threshold voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(V_T)$</tex> of Oxide Semiconductor (OS) FETs for twotransistor (2T) gain-cell memories (GC). By leveraging Interface Dipole (ID) eng. for Indium-Tungsten-Oxide (IWO) FETs, we achieve a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\sim 450-500 \text{mV} V_T$</tex> increase compared to the standard <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{HfO}_2$</tex> (STD), maintaining this <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta V_T$</tex> from 8°C to cryogenic temperatures. ID engineered (ID engd.) GCs exhibit good reliability, showing a ~60 mV shift under worst-case DC positive-bias stress (PBS) at 85°C. This approach is demonstrated across other OS such as Indium-Oxide, Indium-Tin-Oxide, and Indium-Gallium-Zinc-Oxide and at short channel lengths (sub-100 nm). Finally, simulations indicate that ID <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_T$</tex> tuning reduces GC refresh energy by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\sim 50,000 \times$</tex> compared to STD, enabling energy-efficient GC.