Cygnus: A 1 GHz Heterogeneous Octa-Core RISC-V Vector Processor for DSP
We introduce Cygnus, an energy-efficient octa-core RISC-V vector processor compliant with the RVV 1.0 specification targeting digital signal processing (DSP) applications. This chiplet features dynamic instruction scheduling with short vector lengths at the vector core level and a big/little architecture with tightly-coupled memory at the SoC level, facilitating efficient streaming data flow across cores. Cygnus demonstrates a high average utilization of 90% across GEMM and CONV kernels, achieving leading energy efficiencies of 414 GOPS/W for INT8 GEMM and 109 GFLOPS/W for FP32 GEMM. In a representative computer vision kernel implementing denoising using a non-local means algorithm, the chiplet delivers a latency of 3.7 ms with an energy consumption of 518 μJ/ frame.
Authors
- Daniel Grubb
- Yakun Sophia Shao (ORCID: https://orcid.org/0000-0003-1811-5407)
- Jerry Zhao (ORCID: https://orcid.org/0000-0002-9307-2956)
- Kevin Anderson (ORCID: https://orcid.org/0000-0002-1166-7957)
- Krste Asanović (ORCID: https://orcid.org/0000-0003-0754-3975)
- Borivoje Nikolić (ORCID: https://orcid.org/0000-0003-2324-1715)
- Yufeng Chi (ORCID: https://orcid.org/0000-0002-3020-670X)
- Vikram Jain (ORCID: https://orcid.org/0000-0002-1267-1683)
- Ella Schwarz
- Ken Ho
Institutions
- University of California, Berkeley (US)
Publication Details
- Published
- 2025-06-08
- DOI
- https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075041
- Citations
- 2
- Primary Topic
- Image Processing Techniques and Applications
- Type
- article
- Field-Weighted Citation Impact
- 2.27